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  • What is metastability? - Electrical Engineering Stack Exchange
    A metastable state is similar to an unstable equilibrium A common example of an unstable equilibrium is an inverted pendulum If you can balance the pendulum in a vertical position, that is a stable state However, if anything pushes the lever to either side (air currents or ground vibrations, for example), the pendulum will not restore itself to the vertical position, it will fall down
  • How does the second flip-flop in a naive synchronizer prevent a . . .
    In this very nice answer it's explained that, fundamentally, a two flip-flop synchronizer's basic operation is to prevent the propagation of a metastable state (effectively, an invalid logic level) from propagating down a system
  • digital logic - What is the metastable state of an SR latch . . .
    Think of the metastable state described as being like a marble perched precariously at the peak of a gaussian like curve It could just sit there, indefinitely But any "nudge" sends it down one slope of the other to one of the two stable states
  • If a flip flop has a setup violation and goes metastable, is it . . .
    To avoid having a flip flop go metastable, it is necessary to comply not only with setup and hold times for the data wire, but also with minimum high- and low- times for the clock, and with minimum active times ande minimum release-to-clock times for any asynchronous inputs
  • Metastable state when S = R = 1 in SR Latch?
    According to wikibooks, under the section SR Latch, S = R = 1 is a metastable state The following things are mentioned under the heading When both inputs are high at once, however, there is a pr
  • After metastability, does the value eventually settle to the correct . . .
    Now -- in practice, the output will settle to a value; because the metastable flop-flop is a high gain circuit starting from an unstable equilibrium point, the settling is achieved exponentially -- as the signal deviates from the balance point, it changes faster and faster
  • FPGA metastability when going from a slow clock to faster clock?
    It doesn't matter which of the two clocks is slower This is a problem whenever you have two asynchronous clocks Any signal that crosses from one clock domain to the other needs treatment for metastability
  • Metastability concern in bang-bang phase detector
    This section (13 4 1) discusses bang-bang phase detector As highlighted in the picture above, it mentions that Dout might be metastable, and indicates that the metastability effect is analyzed in the article Analysis and modeling of bang-bang clock and data recovery circuits The picture below shows the relevant part of the article
  • Metastability simulation - Electrical Engineering Stack Exchange
    Metastability is generally not oscillation, but the signal , not an inverter, hovering around 50% of rail for an extended period of time before settling to one or other state Just a few weeks ago, I successfully observed metastability in an LtSpice simulation I googled for a transistor level model of a d-latch, and then used a binary search for the exact input voltage that would make it
  • digital logic - Why would an intermediate voltage level cause a . . .
    If you feed a signal to one side of an R-S latch that is supposed to change the state but the signal is close to the (voltage and time) threshold of what will change the state, it might sit in a metastable state for a very long and unpredictable time in terms of normal nanosecond propagation delays





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